1. Technical Field
The present invention relates generally to data communications. More particularly, the present invention relates to equalization circuitry for data communications.
2. Description of the Background Art
High-speed data links are used to communicate data between devices in a system. Serial interface protocols have been developed at increasingly fast data rates for such high-speed links. Examples of industry-standard protocols for serial interfaces include PCI Express® (Peripheral Component Interconnect Express), XAUI (X Attachment Unit Interface), sRIO (serial Rapid IO), and others.
Conventional equalization techniques include continuous time linear equalization (CTLE). As the operating speed of the high-speed data links increases to rates which are tens of gigabits per second (Gbps) or more, sophisticated equalization schemes, such as decision feedback equalization (DFE), has become more commonly used in order to compensate for high-frequency signal loss. However, such complex techniques typically require circuitry that consumes a large amount of power and may be less flexible in terms of meeting requirements for various types of applications.
It is highly desirable to improve data communications. In particular, it is highly desirable to improve equalization techniques to support high-speed data communications.